AMD
‘Article’
Moving on to Strix Halo (STX Halo), the document lists 16 cores and 32 threads based on Zen5 architecture. Similarly to
STX would feature 1MB per core, which means 16MB of L2 cache and 32MB of L3 cache per CCD. Presumably, this
APU will feature two CCDs, each with 8 Zen5 cores. The Strix Halo will also feature 32MB of MALL Cache, which should
function similarly to Infinity Cache.
The APU is to support the XDNA2 processor for Al, offering up to 60 TOPS. It is worth noting that the figure is just for the NPU
part, not the CPU & GPU. The Halo will feature support for up to DP 2.1 UHBR20 mode.
The Halo supports 256-bit LPDDR5X-8000 memory, while Point supports up to LPDDR5x-7500 judging from the
slides. According to the specs, the Halo has a 70W TDP by default, but it is mentioned that it will work up to 130W. The
Halo uses an FP11 socket.
AMD is scheduled to deliver a keynote at Computex, possibly involving updates to Zen5 for desktops and
mobile series. Hopefully, this will also include the Ryzen 9000 aka Strix series.